Temperature & Humidity Reliability Study of a WLCSP Package with CB2 Trench

Sooraj Karnik

This paper presents a temperature and humidity (TH) stress reliability study on a wafer-level chip scale package (WLCSP) with Crack-Barrier2 (CB2) trench structure built using fab process technology at 55nm node. The study was devised to respond to a customer return issue involving exposure to TH stress. It describes a Resistor-Capacitor Oscillator (RCO) frequency based failure mode observed with the CB2 trench structure in TH stress. For the failure mechanism, it then formulates a Weibull reliability acceleration model with two different humidity stress conditions used in the study, based on Peck’s law. The paper empirically calculates a humidity acceleration parameter from the model. It compares and contrasts the parameter obtained from our study with Peck’s original calculations. It then uses the model formulation to show that the customer 10 years use reliability risk is low for TH exposure for RCO frequency failure mode even with compromised CB2 trench structure.